During fabrication of a semiconductor device, etching processes are utilized to form contact openings (also referred to as “via through-holes” or simply “vias”) and other features (e.g., trenches) through an inter layer dielectric (“ILD”) to form electrical interconnects. Such etching processes typically leave behind etch residue, which may adhere to the inner sidewalls of a contact opening. Also, in cases wherein an ashing process is performed to remove a patterned photoresist utilized to define the contact openings, the ashing process can generate additional contaminants that lodge within the contact openings and within the ILD. Therefore, to remove etch residue and other contaminants, the semiconductor device is typically subjected to a wet or dry clean process. In the case of a wet clean process, the semiconductor device is flooded with an aqueous cleaning solvent, such as hydrofluoric acid diluted in water. The solvent effectively dissolves and washes away etch residue and other contaminants from within the contact openings and thus helps to ensure that a low resistance contact can be achieved during subsequent fabrication steps.
ILDs are increasingly being formed from ultra low-k (“ULK”) materials having relatively high porosities; e.g., porosities exceeding 10% and, in certain cases, approaching 50%. Advantageously, highly porous ULK materials provide superior electrical isolation and thus permit the interconnect capacitance to be minimized. However, when formed from a highly porous ULK material, the ILD tends to absorb a substantial volume of water during post-etch wet clean processes of the type described above. In particular, water from the aqueous cleaning solvent is absorbed through the porous sidewalls of the contact openings and often diffuses a significant distance into the body of the porous ILD. Although some of the absorbed water may evaporate during subsequent fabrication steps (e.g., liner degas), a portion of the absorbed water remains within the porous ILD as residual moisture. As the semiconductor device is subjected to thermal cycling during further processing steps, the residual water reacts with and oxidizes the metal liner subsequently deposited over the sidewalls of the contact openings and trenches. Oxidation decreases the effectiveness of the metal liner as a barrier to the conductive (e.g., copper) plug later formed within the contact opening. In addition, oxidation of the metal liner can also result in an undesirable increase in line-to-line capacitance when the metal liner is formed from a metal (e.g., tantalum) that becomes a high k dielectric upon oxidation. Although the porous ILD can be dehydrated by performing an annealing process wherein the semiconductor device is exposed to elevated temperatures (e.g., 150 to 500 degrees Celsius) for a prolonged period of time prior to metallization, the performance of such a prolonged anneal is time consuming and can result in an undesirable deformation of the ILD proximate the contact openings. The thermal budget of the transistors, already formed, may also limit the temperatures used for interconnection fabrication.
There thus exists an ongoing need to provide embodiments of a method for fabricating a semiconductor device including a drying process that removes residual water and other contaminants from within a highly porous material, such as an inter layer dielectric formed from a porous ultra low-k material, without prolonged exposure of the semiconductor device to high temperatures. Preferably, embodiments of the semiconductor fabrication method would include a drying technique that can be readily incorporated into existing wet cleaning process utilized to remove etch residue and other contaminants from the inner sidewalls of features (e.g., contact openings) formed in an inter layer dielectric. Other desirable features and characteristics of the present invention will become apparent from the subsequent Detailed Description and the appended Claims, taken in conjunction with the accompanying Drawings and this Background.